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| pps2sdp [2023/03/02 00:04] – [ts2phc] millerjs | pps2sdp [2024/11/14 02:30] (current) – external edit 127.0.0.1 |
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| ====== PPS to SDP ====== | ====== PPS to SDP ====== |
| There are a few effective ways to feed a PPS signal from a GNSS receiver (or other time source) into a computer. A few examples: on a system with a "standard" serial port, the DCD pin can be used very effectively, on many single board computers (e.g. Raspberry Pi et al) a GPIO pin can be used for PPS input. Purpose built hardware exists as well, network cards like the Solarflare SFN6322F have SMA connectors specifically for PPS in and out. In today's case, we're going to be looking at the Intel i210 ethernet controller. A humble PCIe gigabit network interface that just happens to have four software defined pins (thus, SDP) that can be used for hardware timestamping via IEEE1588 and IEEE 802.1AS. | There are a few effective ways to feed a PPS((pulse per second)) signal from a GNSS receiver, or other precision pulse source, into a computer. A few examples: systems with a "standard" serial port can use the DCD pin, and on many single board computers (Raspberry Pi et al) a GPIO pin can sometimes be used for PPS input. Purpose built hardware exists as well, network cards like the Solarflare SFN6322F have SMA connectors specifically for PPS in and out. In this article, we're going to be looking at the Intel i210 ethernet controller. A humble PCIe gigabit network interface from 2012 that was designed with four software defined pins (SDPs) that can be used for hardware timestamping via IEEE1588 and IEEE 802.1AS. |
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| {{::i210-sdp-pins.png?259 |}}The i210 and its software defined pins are well supported by the LinuxPTP project, and a number of folks have already put together some documentation on using its SDPs as a way to get hardware timestamps from a GNSS receiver into software like chrony or NTPsec. | {{::i210-sdp-pins.png?259 |}}The i210 and its software defined pins are well supported by the LinuxPTP project, and a number of folks have already put together some documentation on using its SDPs as a way to get hardware timestamps from a GNSS receiver into software like chrony or NTPsec. |
| * [[https://chrony.tuxfamily.org/examples.html#_server_using_reference_clock_on_nic|Chrony documentation - Server using reference clock on NIC]] | * [[https://chrony.tuxfamily.org/examples.html#_server_using_reference_clock_on_nic|Chrony documentation - Server using reference clock on NIC]] |
| * [[https://docs.nvidia.com/networking/display/NVIDIA5TTechnologyUserManualv10/5T+Technology+(PTP,+SyncE,+and+more)+User+Manual|nvidia 5T user manual]] | * [[https://docs.nvidia.com/networking/display/NVIDIA5TTechnologyUserManualv10/5T+Technology+(PTP,+SyncE,+and+more)+User+Manual|nvidia 5T user manual]] |
| | * [[https://febo.com/pipermail/time-nuts_lists.febo.com/2023-February/107321.html|This thread from the TimeNuts mailing list]] |
| | * [[https://wiki.gentoo.org/wiki/Chrony_with_hardware_timestamping|This gentoo wiki page has some good stuff]] |
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| ===== Software ===== | ===== Software ===== |
| event index 0 at 1677526115.935919744 | event index 0 at 1677526115.935919744 |
| </code> | </code> |
| | You may notice that there are only 5 seconds represented here - that's because in each timepulse there are two events, one for the rising edge, and then another for the falling edge, 100ms later. The i210 only reports both edges. |
| ==== ts2phc ==== | ==== ts2phc ==== |
| Part of the [[https://linuxptp.nwtime.org/about/|LinuxPTP]] project, [[https://linuxptp.nwtime.org/documentation/ts2phc/|ts2phc]] is a tool that synchronizes time stamps coming over the SDP with the PHC. The following command can be used to sync the incoming timestamps with the PHC. The system clock must be roughly correct for this to work correctly. | Part of the [[https://linuxptp.nwtime.org/about/|LinuxPTP]] project, [[https://linuxptp.nwtime.org/documentation/ts2phc/|ts2phc]] is a tool that synchronizes time stamps coming over the SDP with the PHC. The following command can be used to sync the incoming timestamps with the PHC. The system clock must be roughly correct for this to work correctly. |
| max_frequency 1000000 | max_frequency 1000000 |
| step_threshold 0.05 | step_threshold 0.05 |
| [enp2s0] | leapfile /usr/share/zoneinfo/leap-seconds.list |
| | [/dev/ptp0] |
| ts2phc.channel 0 | ts2phc.channel 0 |
| ts2phc.extts_polarity both | ts2phc.extts_polarity both |
| ts2phc[2226.309]: /dev/ptp0 offset 1804 s2 freq -8469 | ts2phc[2226.309]: /dev/ptp0 offset 1804 s2 freq -8469 |
| </code> | </code> |
| | (Note: in this instance, I've used ''-l 7'' for more verbose logging, which can be beneficial for diagnostic purposes.) |
| ==== phc2sys ==== | ==== phc2sys ==== |
| Also a part of LinuxPTP, [[https://linuxptp.nwtime.org/documentation/phc2sys/|phc2sys]] is a utility included as part of the linuxptp project for syncing clocks - usually syncing PHC to SYS. | Also a part of LinuxPTP, [[https://linuxptp.nwtime.org/documentation/phc2sys/|phc2sys]] is a utility included as part of the linuxptp project for syncing clocks - usually syncing PHC to SYS. This tool is run after ''ts2phc'' to align the PHC with the system clock. |
| |
| <code>phc2sys -c eth0 -s CLOCK_REALTIME -O +37 -m -q</code> | <code>phc2sys -c /dev/ptp0 -s CLOCK_REALTIME -O +37 -m -q</code> |
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| The +37 second offset aligns the clock with [[https://en.wikipedia.org/wiki/International_Atomic_Time|TAI]]. | The +37 second offset aligns the clock with [[https://en.wikipedia.org/wiki/International_Atomic_Time|TAI]]. |
| |
| | === Example Usage === |
| <code> | <code> |
| ~# phc2sys -c eth0 -s CLOCK_REALTIME -O +37 -m -q | ~ # phc2sys -c /dev/ptp0 -s CLOCK_REALTIME -O +37 -m -q |
| phc2sys[2638.904]: eth0 sys offset 22822213 s0 freq -9007 delay 2054 | phc2sys[2335.481]: /dev/ptp0 sys offset -148 s0 freq -10113 delay 2055 |
| phc2sys[2639.905]: eth0 sys offset 22822277 s1 freq -8943 delay 2067 | phc2sys[2336.481]: /dev/ptp0 sys offset -161 s2 freq -10126 delay 2064 |
| phc2sys[2640.905]: eth0 sys offset -5994 s2 freq -14937 delay 2097 | phc2sys[2337.481]: /dev/ptp0 sys offset -184 s2 freq -10310 delay 2065 |
| phc2sys[2641.905]: eth0 sys offset 7 s2 freq -10734 delay 2071 | phc2sys[2338.481]: /dev/ptp0 sys offset 38 s2 freq -10143 delay 2068 |
| phc2sys[2642.906]: eth0 sys offset 1780 s2 freq -8959 delay 2061 | phc2sys[2339.482]: /dev/ptp0 sys offset 47 s2 freq -10123 delay 2042 |
| phc2sys[2643.906]: eth0 sys offset 1789 s2 freq -8416 delay 2101 | phc2sys[2340.482]: /dev/ptp0 sys offset 69 s2 freq -10087 delay 2071 |
| phc2sys[2644.906]: eth0 sys offset 1275 s2 freq -8393 delay 2071 | phc2sys[2341.482]: /dev/ptp0 sys offset 43 s2 freq -10092 delay 2077 |
| phc2sys[2645.907]: eth0 sys offset 734 s2 freq -8552 delay 2071 | phc2sys[2342.483]: /dev/ptp0 sys offset 6 s2 freq -10116 delay 2074 |
| phc2sys[2646.907]: eth0 sys offset 355 s2 freq -8711 delay 2071 | phc2sys[2343.483]: /dev/ptp0 sys offset -5 s2 freq -10125 delay 2070 |
| phc2sys[2647.907]: eth0 sys offset 115 s2 freq -8844 delay 2071 | phc2sys[2344.483]: /dev/ptp0 sys offset 5 s2 freq -10117 delay 2058 |
| phc2sys[2648.907]: eth0 sys offset -26 s2 freq -8951 delay 2041 | phc2sys[2345.483]: /dev/ptp0 sys offset 2 s2 freq -10118 delay 2069 |
| phc2sys[2649.908]: eth0 sys offset -4 s2 freq -8936 delay 2101 | phc2sys[2346.484]: /dev/ptp0 sys offset -7 s2 freq -10127 delay 2069</code> |
| phc2sys[2650.908]: eth0 sys offset 8 s2 freq -8926 delay 2071 | |
| phc2sys[2651.908]: eth0 sys offset -24 s2 freq -8955 delay 2071 | |
| phc2sys[2652.909]: eth0 sys offset -19 s2 freq -8957 delay 2071 | |
| phc2sys[2653.909]: eth0 sys offset -11 s2 freq -8955 delay 2071 | |
| phc2sys[2654.909]: eth0 sys offset -10 s2 freq -8957 delay 2081 | |
| phc2sys[2655.910]: eth0 sys offset 16 s2 freq -8934 delay 2071 | |
| phc2sys[2656.910]: eth0 sys offset -6 s2 freq -8952 delay 2071 | |
| phc2sys[2657.910]: eth0 sys offset -8 s2 freq -8955 delay 2076 | |
| phc2sys[2658.910]: eth0 sys offset -12 s2 freq -8962 delay 2101 | |
| phc2sys[2659.911]: eth0 sys offset 23 s2 freq -8930 delay 2071 | |
| phc2sys[2660.911]: eth0 sys offset 16 s2 freq -8930 delay 2071 | |
| phc2sys[2661.911]: eth0 sys offset -7 s2 freq -8949 delay 2071 | |
| phc2sys[2662.912]: eth0 sys offset -45 s2 freq -8989 delay 2036 | |
| phc2sys[2663.912]: eth0 sys offset 16 s2 freq -8941 delay 2071 | |
| phc2sys[2664.912]: eth0 sys offset 23 s2 freq -8929 delay 2071 | |
| </code> | |
| |
| ==== chrony ==== | ==== chrony ==== |
